ECE 552 Project

ECE-552: Microprocessor Architecture

The final project for ECE-552 was to implement a processor via schematic design. Groups were formed from three individuals and were instructed to implement a given instruction set using a cache. Each gate we used had a preset cost and delay. Below is a table representing the final results of all groups; our group is in highlighted in red. Due to clever logic tricks, resource management, and cost analysis, our group was able not only to obtain the fastest speed but also the lowest cost.

Group Members	System	Cache	Clock (ns)	Max Cycles	CPI	Demo Time	Cost
Sondra Renly John Schmitt James Speirs	Works	Works	55	5	4.05	314	10662
Anand Chhatpar Ayax Sevilla Douglas Suthers	Works	Works	64	6	4.2	365	11120
Cheraladhan Ganesan P. Gopalakrishnan Eun-Sun Kim	Works	No	48	5	3.79	243	7685
Lirim Ashiku Dan Gibson Kevin Strouse	Works	Works	39	4	4.04	180.2	12305
Jake Adriaens Brad Colvin Will Danen	Works	Works	58	5	4.05	322	16844
Jeffrey Haack Nick Heiting Richard Stern	Works	No	59	3	2.81	226.6	12944
Bryan Berns Jeremy Baumgartner Bill Stube	Works	Works	34	3	2.31	118	6566
HongHong Chang Zhiyu Liu Stanley Nangoy	Works	No	44	5	3.96	229	24954
Paul Anheier Jeremy Lawinger Scott Wiese	Works	No	42	-	3.49	202	9980
Jake Petranek Justin Shepard Anuj Subhash Patel	No	No	48	5	3.99	-	8414
Bryan Lang Tim Larson Ryan Monfils	Works	Works	48	5	3.78	315	11652
Ben Davenport Chris Durheim Brian Eriksson	Works	No	60	5	4.05	333	12424
Hsin-chi Chan Derek Daun Ben Gartner	No	No	60	5	-	-	10570
Fred Klumb Nolan Salzmann Daniel Weichsel	Works	Works	57	7	4.25	378	7980